tartan_arch/
x86_64.rs

1//! Architecture-specific primitives for 64-bit x86 processors.
2
3use crate::{model_specific_register_access, simple_register_access};
4use tartan_bitfield::bitfield;
5
6pub mod protection;
7
8
9bitfield! {
10    /// `CR8`: System control register for controlling interrupts based on priority.
11    ///
12    /// Getters and setters for this structure only access a value in memory, not the
13    /// register itself. Use the [`get`](Self::get) and [`set`](Self::set) methods to
14    /// work with the actual register.
15    pub struct ControlRegister8(usize) {
16        /// `CR8.TPL`: Threshold for blocking low-priority interrupts. Lower values are
17        /// higher priority.
18        [0..4] pub task_priority_level: u8,
19    }
20}
21
22simple_register_access!(ControlRegister8, "cr8");
23
24
25bitfield! {
26    /// `IA32_EFER`: Model-specific register that controls features relating to 64-bit
27    /// operation.
28    pub struct ExtendedFeatureEnableRegister(u64) {
29        /// `IA32_EFER.SCE`: Support `SYSCALL`/`SYSRET` in 64-bit mode.
30        [0] pub syscall,
31        /// `IA32_EFER.LME`: Support 64-bit mode.
32        [8] pub long_mode_enabled,
33        /// `IA32_EFER.LMA`: Indicates 64-bit mode is active. Read-only.
34        ///
35        /// This is logically the equivalent to `[Self::long_mode_enabled] &
36        /// [ControlRegister0::paging]`.
37        [10] pub long_mode_active,
38        /// `IA32-EFER.NXE`: Support no-execute (NX) bit in page tables.
39        [11] pub no_execute,
40    }
41}
42
43model_specific_register_access!(ExtendedFeatureEnableRegister, 0xc000_0080_u32);
tartan_arch/x86_64.rs

tartan_arch/
x86_64.rs
