Module tartan_arch::x86_common::paging

Available on x86 or x86-64 only.

Support for virtual memory paging.

Structs

• ControlRegister2
  CR2: Contains the address that triggered a page fault.
• ControlRegister3
  CR3: System control register that contains the top-level page table address and two associated caching flags.
• Level1PageTableEntry
  Bottom-level page table entry that maps a single 4KB page.
• Level2PageTableEntry
  Second-level page table (page directory) entry that either points to a bottom-level page table or directly maps a 2MB/4MB page.

Traits

• DirectPageTableEntry
  An page table entry (any level) that directly maps a page.
• GenericPageTableEntry
  An entry in a page table at any level.
• HybridPageTableEntry
  A page table entry (any level) that either directly maps a page or points to another page table.