Available on x86 or x86-64 only.
Expand description
Support for virtual memory paging.
Structs§
- Control
Register2 CR2: Contains the address that triggered a page fault.- Control
Register3 CR3: System control register that contains the top-level page table address and two associated caching flags.- Level1
Page Table Entry - Bottom-level page table entry that maps a single 4KB page.
- Level2
Page Table Entry - Second-level page table (page directory) entry that either points to a bottom-level page table or directly maps a 2MB/4MB page.
Traits§
- Direct
Page Table Entry - An page table entry (any level) that directly maps a page.
- Generic
Page Table Entry - An entry in a page table at any level.
- Hybrid
Page Table Entry - A page table entry (any level) that either directly maps a page or points to another page table.