Struct tartan_arch::x86_common::features::BasicFeatures

pub struct BasicFeatures(/* private fields */);

Available on x86 or x86-64 only.

Primary feature list returned in CPUID.01H:ECX+EDX.

Implementations

impl BasicFeatures

pub fn on_chip_fpu(&self) -> bool

FPU: The processor has a built-in x87 floating-point unit

pub fn virtual_8086_extensions(&self) -> bool

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

pub fn debugging_extensions(&self) -> bool

DE: Supports breaking on I/O and on accessing debug registers DR4–DR5.

pub fn page_size_extension(&self) -> bool

PSE: Supports 4MB virtual memory pages and the dirty flag.

pub fn time_stamp_counter(&self) -> bool

TSC: Supports reading the processor’s timestamp with RDTSC.

pub fn model_registers(&self) -> bool

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

pub fn physical_address_extension(&self) -> bool

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

pub fn machine_check_exception(&self) -> bool

MCE: Defines an exception (18) for reporting internal processor errors.

pub fn compare_exchange_64bit(&self) -> bool

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

pub fn on_chip_apic(&self) -> bool

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

pub fn sysenter(&self) -> bool

SEP: Supports the SYSENTER/SYSEXIT instructions.

pub fn memory_type_range_registers(&self) -> bool

MTRR: Has memory type range registers.

pub fn global_pages(&self) -> bool

PGE: Supports global pages, which are available in all task contexts

pub fn machine_check_architecture(&self) -> bool

MCA: Supports extended features for reporting internal processor errors.

pub fn conditional_move(&self) -> bool

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

pub fn page_attribute_table(&self) -> bool

PAT: Supports page attribute tables.

pub fn page_size_extension_36bit(&self) -> bool

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

pub fn serial_number(&self) -> bool

PSN: Supports retrieving a processor serial number with the CPUID instruction.

pub fn cache_line_flush(&self) -> bool

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

pub fn debug_store(&self) -> bool

DS: Supports writing debug information to memory.

pub fn thermal_power_management(&self) -> bool

ACPI: Supports thermal monitoring and power management with software.

pub fn mmx(&self) -> bool

MMX: Supports MMX instructions.

pub fn fpu_save(&self) -> bool

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

pub fn sse(&self) -> bool

SSE: Supports SSE instructions.

pub fn sse_2(&self) -> bool

SSE2: Supports SSE2 instructions.

pub fn self_snoop(&self) -> bool

The processor can snoop on its own cache line. This helps deal with certain memory issues.

pub fn max_apic_id_field(&self) -> bool

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

pub fn thermal_monitor(&self) -> bool

TM: Has thermal monitor control circuitry (TCC).

pub fn pending_break_enable(&self) -> bool

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

pub fn sse_3(&self) -> bool

SSE3: Supports SSE3 instructions.

pub fn carryless_multiply_64bit(&self) -> bool

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

pub fn debug_store_64bit(&self) -> bool

DTES64: Supports 64-bit addresses for the debug store.

pub fn monitor(&self) -> bool

MONITOR: Supports the MONITOR/MWAIT instructions.

pub fn permission_qualified_debug_store(&self) -> bool

DS-CPL: Supports saving the permission level with data written to the debug store.

pub fn virtual_machine_extensions(&self) -> bool

VMX: Supports virtual machine extensions.

pub fn safer_mode_extensions(&self) -> bool

SMX: Supports safer-mode extensions

pub fn enhanced_speedstep(&self) -> bool

EIST: Supports enhanced SpeedStep throttling.

pub fn thermal_monitor_2(&self) -> bool

Supports the TM2 thermal monitor interface.

pub fn supplemental_sse_3(&self) -> bool

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

pub fn l1_context_id(&self) -> bool

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

pub fn debug_interface_model_register(&self) -> bool

SDBG: Supports an MSR for chip debugging.

pub fn fused_multiply_add(&self) -> bool

FMA: Supports fused multiply-add SSE instructions.

pub fn compare_exchange_128bit(&self) -> bool

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

pub fn chipset_task_priority_control(&self) -> bool

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

pub fn monitor_debug_capabilities_register(&self) -> bool

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

pub fn process_context_ids(&self) -> bool

PCID: Supports process-context IDs.

pub fn memory_mapped_prefetch(&self) -> bool

DCA: Supports prefetching memory-mapped data from a device.

pub fn sse_4_1(&self) -> bool

SSE4_1: Supports SSE4.1 instructions.

pub fn sse_4_2(&self) -> bool

SSE4_2: Supports SSE4.2 instructions.

pub fn apic_x2(&self) -> bool

x2APIC: Supports the enhanced “x2” interface for the APIC.

pub fn byte_swap_move(&self) -> bool

Supports byte swapping with the MOVBE instruction.

pub fn count_bits(&self) -> bool

Supports counting the set bits in a value with the POPCNT instruction.

pub fn apic_timestamp_deadline(&self) -> bool

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

pub fn aes(&self) -> bool

AESNI: Supports AES acceleration instructions.

pub fn extended_state_save(&self) -> bool

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

pub fn extended_state_save_enabled(&self) -> bool

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

pub fn avx(&self) -> bool

AVX: Supports AVX instructions.

pub fn float_16_conversion(&self) -> bool

F16C: Supports conversion instructions for 16-bit floats.

pub fn random(&self) -> bool

Supports random number generation with the RDRAND instruction.

pub fn set_on_chip_fpu(&mut self, value: bool)

FPU: The processor has a built-in x87 floating-point unit

pub fn with_on_chip_fpu(&mut self, value: bool) -> Self

FPU: The processor has a built-in x87 floating-point unit

pub fn set_virtual_8086_extensions(&mut self, value: bool)

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

pub fn with_virtual_8086_extensions(&mut self, value: bool) -> Self

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

pub fn set_debugging_extensions(&mut self, value: bool)

DE: Supports breaking on I/O and on accessing debug registers DR4–DR5.

pub fn with_debugging_extensions(&mut self, value: bool) -> Self

DE: Supports breaking on I/O and on accessing debug registers DR4–DR5.

pub fn set_page_size_extension(&mut self, value: bool)

PSE: Supports 4MB virtual memory pages and the dirty flag.

pub fn with_page_size_extension(&mut self, value: bool) -> Self

PSE: Supports 4MB virtual memory pages and the dirty flag.

pub fn set_time_stamp_counter(&mut self, value: bool)

TSC: Supports reading the processor’s timestamp with RDTSC.

pub fn with_time_stamp_counter(&mut self, value: bool) -> Self

TSC: Supports reading the processor’s timestamp with RDTSC.

pub fn set_model_registers(&mut self, value: bool)

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

pub fn with_model_registers(&mut self, value: bool) -> Self

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

pub fn set_physical_address_extension(&mut self, value: bool)

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

pub fn with_physical_address_extension(&mut self, value: bool) -> Self

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

pub fn set_machine_check_exception(&mut self, value: bool)

MCE: Defines an exception (18) for reporting internal processor errors.

pub fn with_machine_check_exception(&mut self, value: bool) -> Self

MCE: Defines an exception (18) for reporting internal processor errors.

pub fn set_compare_exchange_64bit(&mut self, value: bool)

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

pub fn with_compare_exchange_64bit(&mut self, value: bool) -> Self

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

pub fn set_on_chip_apic(&mut self, value: bool)

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

pub fn with_on_chip_apic(&mut self, value: bool) -> Self

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

pub fn set_sysenter(&mut self, value: bool)

SEP: Supports the SYSENTER/SYSEXIT instructions.

pub fn with_sysenter(&mut self, value: bool) -> Self

SEP: Supports the SYSENTER/SYSEXIT instructions.

pub fn set_memory_type_range_registers(&mut self, value: bool)

MTRR: Has memory type range registers.

pub fn with_memory_type_range_registers(&mut self, value: bool) -> Self

MTRR: Has memory type range registers.

pub fn set_global_pages(&mut self, value: bool)

PGE: Supports global pages, which are available in all task contexts

pub fn with_global_pages(&mut self, value: bool) -> Self

PGE: Supports global pages, which are available in all task contexts

pub fn set_machine_check_architecture(&mut self, value: bool)

MCA: Supports extended features for reporting internal processor errors.

pub fn with_machine_check_architecture(&mut self, value: bool) -> Self

MCA: Supports extended features for reporting internal processor errors.

pub fn set_conditional_move(&mut self, value: bool)

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

pub fn with_conditional_move(&mut self, value: bool) -> Self

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

pub fn set_page_attribute_table(&mut self, value: bool)

PAT: Supports page attribute tables.

pub fn with_page_attribute_table(&mut self, value: bool) -> Self

PAT: Supports page attribute tables.

pub fn set_page_size_extension_36bit(&mut self, value: bool)

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

pub fn with_page_size_extension_36bit(&mut self, value: bool) -> Self

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

pub fn set_serial_number(&mut self, value: bool)

PSN: Supports retrieving a processor serial number with the CPUID instruction.

pub fn with_serial_number(&mut self, value: bool) -> Self

PSN: Supports retrieving a processor serial number with the CPUID instruction.

pub fn set_cache_line_flush(&mut self, value: bool)

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

pub fn with_cache_line_flush(&mut self, value: bool) -> Self

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

pub fn set_debug_store(&mut self, value: bool)

DS: Supports writing debug information to memory.

pub fn with_debug_store(&mut self, value: bool) -> Self

DS: Supports writing debug information to memory.

pub fn set_thermal_power_management(&mut self, value: bool)

ACPI: Supports thermal monitoring and power management with software.

pub fn with_thermal_power_management(&mut self, value: bool) -> Self

ACPI: Supports thermal monitoring and power management with software.

pub fn set_mmx(&mut self, value: bool)

MMX: Supports MMX instructions.

pub fn with_mmx(&mut self, value: bool) -> Self

MMX: Supports MMX instructions.

pub fn set_fpu_save(&mut self, value: bool)

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

pub fn with_fpu_save(&mut self, value: bool) -> Self

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

pub fn set_sse(&mut self, value: bool)

SSE: Supports SSE instructions.

pub fn with_sse(&mut self, value: bool) -> Self

SSE: Supports SSE instructions.

pub fn set_sse_2(&mut self, value: bool)

SSE2: Supports SSE2 instructions.

pub fn with_sse_2(&mut self, value: bool) -> Self

SSE2: Supports SSE2 instructions.

pub fn set_self_snoop(&mut self, value: bool)

The processor can snoop on its own cache line. This helps deal with certain memory issues.

pub fn with_self_snoop(&mut self, value: bool) -> Self

The processor can snoop on its own cache line. This helps deal with certain memory issues.

pub fn set_max_apic_id_field(&mut self, value: bool)

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

pub fn with_max_apic_id_field(&mut self, value: bool) -> Self

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

pub fn set_thermal_monitor(&mut self, value: bool)

TM: Has thermal monitor control circuitry (TCC).

pub fn with_thermal_monitor(&mut self, value: bool) -> Self

TM: Has thermal monitor control circuitry (TCC).

pub fn set_pending_break_enable(&mut self, value: bool)

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

pub fn with_pending_break_enable(&mut self, value: bool) -> Self

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

pub fn set_sse_3(&mut self, value: bool)

SSE3: Supports SSE3 instructions.

pub fn with_sse_3(&mut self, value: bool) -> Self

SSE3: Supports SSE3 instructions.

pub fn set_carryless_multiply_64bit(&mut self, value: bool)

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

pub fn with_carryless_multiply_64bit(&mut self, value: bool) -> Self

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

pub fn set_debug_store_64bit(&mut self, value: bool)

DTES64: Supports 64-bit addresses for the debug store.

pub fn with_debug_store_64bit(&mut self, value: bool) -> Self

DTES64: Supports 64-bit addresses for the debug store.

pub fn set_monitor(&mut self, value: bool)

MONITOR: Supports the MONITOR/MWAIT instructions.

pub fn with_monitor(&mut self, value: bool) -> Self

MONITOR: Supports the MONITOR/MWAIT instructions.

pub fn set_permission_qualified_debug_store(&mut self, value: bool)

DS-CPL: Supports saving the permission level with data written to the debug store.

pub fn with_permission_qualified_debug_store(&mut self, value: bool) -> Self

DS-CPL: Supports saving the permission level with data written to the debug store.

pub fn set_virtual_machine_extensions(&mut self, value: bool)

VMX: Supports virtual machine extensions.

pub fn with_virtual_machine_extensions(&mut self, value: bool) -> Self

VMX: Supports virtual machine extensions.

pub fn set_safer_mode_extensions(&mut self, value: bool)

SMX: Supports safer-mode extensions

pub fn with_safer_mode_extensions(&mut self, value: bool) -> Self

SMX: Supports safer-mode extensions

pub fn set_enhanced_speedstep(&mut self, value: bool)

EIST: Supports enhanced SpeedStep throttling.

pub fn with_enhanced_speedstep(&mut self, value: bool) -> Self

EIST: Supports enhanced SpeedStep throttling.

pub fn set_thermal_monitor_2(&mut self, value: bool)

Supports the TM2 thermal monitor interface.

pub fn with_thermal_monitor_2(&mut self, value: bool) -> Self

Supports the TM2 thermal monitor interface.

pub fn set_supplemental_sse_3(&mut self, value: bool)

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

pub fn with_supplemental_sse_3(&mut self, value: bool) -> Self

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

pub fn set_l1_context_id(&mut self, value: bool)

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

pub fn with_l1_context_id(&mut self, value: bool) -> Self

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

pub fn set_debug_interface_model_register(&mut self, value: bool)

SDBG: Supports an MSR for chip debugging.

pub fn with_debug_interface_model_register(&mut self, value: bool) -> Self

SDBG: Supports an MSR for chip debugging.

pub fn set_fused_multiply_add(&mut self, value: bool)

FMA: Supports fused multiply-add SSE instructions.

pub fn with_fused_multiply_add(&mut self, value: bool) -> Self

FMA: Supports fused multiply-add SSE instructions.

pub fn set_compare_exchange_128bit(&mut self, value: bool)

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

pub fn with_compare_exchange_128bit(&mut self, value: bool) -> Self

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

pub fn set_chipset_task_priority_control(&mut self, value: bool)

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

pub fn with_chipset_task_priority_control(&mut self, value: bool) -> Self

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

pub fn set_monitor_debug_capabilities_register(&mut self, value: bool)

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

pub fn with_monitor_debug_capabilities_register(&mut self, value: bool) -> Self

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

pub fn set_process_context_ids(&mut self, value: bool)

PCID: Supports process-context IDs.

pub fn with_process_context_ids(&mut self, value: bool) -> Self

PCID: Supports process-context IDs.

pub fn set_memory_mapped_prefetch(&mut self, value: bool)

DCA: Supports prefetching memory-mapped data from a device.

pub fn with_memory_mapped_prefetch(&mut self, value: bool) -> Self

DCA: Supports prefetching memory-mapped data from a device.

pub fn set_sse_4_1(&mut self, value: bool)

SSE4_1: Supports SSE4.1 instructions.

pub fn with_sse_4_1(&mut self, value: bool) -> Self

SSE4_1: Supports SSE4.1 instructions.

pub fn set_sse_4_2(&mut self, value: bool)

SSE4_2: Supports SSE4.2 instructions.

pub fn with_sse_4_2(&mut self, value: bool) -> Self

SSE4_2: Supports SSE4.2 instructions.

pub fn set_apic_x2(&mut self, value: bool)

x2APIC: Supports the enhanced “x2” interface for the APIC.

pub fn with_apic_x2(&mut self, value: bool) -> Self

x2APIC: Supports the enhanced “x2” interface for the APIC.

pub fn set_byte_swap_move(&mut self, value: bool)

Supports byte swapping with the MOVBE instruction.

pub fn with_byte_swap_move(&mut self, value: bool) -> Self

Supports byte swapping with the MOVBE instruction.

pub fn set_count_bits(&mut self, value: bool)

Supports counting the set bits in a value with the POPCNT instruction.

pub fn with_count_bits(&mut self, value: bool) -> Self

Supports counting the set bits in a value with the POPCNT instruction.

pub fn set_apic_timestamp_deadline(&mut self, value: bool)

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

pub fn with_apic_timestamp_deadline(&mut self, value: bool) -> Self

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

pub fn set_aes(&mut self, value: bool)

AESNI: Supports AES acceleration instructions.

pub fn with_aes(&mut self, value: bool) -> Self

AESNI: Supports AES acceleration instructions.

pub fn set_extended_state_save(&mut self, value: bool)

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

pub fn with_extended_state_save(&mut self, value: bool) -> Self

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

pub fn set_extended_state_save_enabled(&mut self, value: bool)

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

pub fn with_extended_state_save_enabled(&mut self, value: bool) -> Self

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

pub fn set_avx(&mut self, value: bool)

AVX: Supports AVX instructions.

pub fn with_avx(&mut self, value: bool) -> Self

AVX: Supports AVX instructions.

pub fn set_float_16_conversion(&mut self, value: bool)

F16C: Supports conversion instructions for 16-bit floats.

pub fn with_float_16_conversion(&mut self, value: bool) -> Self

F16C: Supports conversion instructions for 16-bit floats.

pub fn set_random(&mut self, value: bool)

Supports random number generation with the RDRAND instruction.

pub fn with_random(&mut self, value: bool) -> Self

Supports random number generation with the RDRAND instruction.

impl BasicFeatures

pub fn get() -> Self

Retrieve the feature list from the processor using the CPUID instruction.

Trait Implementations

impl Bitfield<u64> for BasicFeatures

fn new(value: T) -> Self

Construct a new bitfield type from its underlying representation

fn value(self) -> T

Unwrap the bitfield into its underlying representation

impl Clone for BasicFeatures

fn clone(&self) -> BasicFeatures

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for BasicFeatures

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for BasicFeatures

fn default() -> BasicFeatures

Returns the “default value” for a type.

impl From<BasicFeatures> for u64

fn from(val: BasicFeatures) -> Self

Converts to this type from the input type.

impl From<u64> for BasicFeatures

fn from(val: u64) -> Self

Converts to this type from the input type.

impl PartialEq for BasicFeatures

fn eq(&self, other: &BasicFeatures) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for BasicFeatures

impl Eq for BasicFeatures

impl StructuralPartialEq for BasicFeatures