#[repr(transparent)]
pub struct BasicFeatures(_);
Available on x86 or x86-64 only.
Expand description

Primary feature list returned in CPUID.01H:ECX+EDX.

Implementations§

FPU: The processor has a built-in x87 floating-point unit

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

DE: Supports breaking on I/O and on accessing debug registers DR4DR5.

PSE: Supports 4MB virtual memory pages and the dirty flag.

TSC: Supports reading the processor’s timestamp with RDTSC.

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

MCE: Defines an exception (18) for reporting internal processor errors.

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

SEP: Supports the SYSENTER/SYSEXIT instructions.

MTRR: Has memory type range registers.

PGE: Supports global pages, which are available in all task contexts

MCA: Supports extended features for reporting internal processor errors.

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

PAT: Supports page attribute tables.

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

PSN: Supports retrieving a processor serial number with the CPUID instruction.

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

DS: Supports writing debug information to memory.

ACPI: Supports thermal monitoring and power management with software.

MMX: Supports MMX instructions.

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

SSE: Supports SSE instructions.

SSE2: Supports SSE2 instructions.

The processor can snoop on its own cache line. This helps deal with certain memory issues.

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

TM: Has thermal monitor control circuitry (TCC).

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

SSE3: Supports SSE3 instructions.

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

DTES64: Supports 64-bit addresses for the debug store.

MONITOR: Supports the MONITOR/MWAIT instructions.

DS-CPL: Supports saving the permission level with data written to the debug store.

VMX: Supports virtual machine extensions.

SMX: Supports safer-mode extensions

EIST: Supports enhanced SpeedStep throttling.

Supports the TM2 thermal monitor interface.

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

SDBG: Supports an MSR for chip debugging.

FMA: Supports fused multiply-add SSE instructions.

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

PCID: Supports process-context IDs.

DCA: Supports prefetching memory-mapped data from a device.

SSE4_1: Supports SSE4.1 instructions.

SSE4_2: Supports SSE4.2 instructions.

x2APIC: Supports the enhanced “x2” interface for the APIC.

Supports byte swapping with the MOVBE instruction.

Supports counting the set bits in a value with the POPCNT instruction.

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

AESNI: Supports AES acceleration instructions.

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

AVX: Supports AVX instructions.

F16C: Supports conversion instructions for 16-bit floats.

Supports random number generation with the RDRAND instruction.

FPU: The processor has a built-in x87 floating-point unit

FPU: The processor has a built-in x87 floating-point unit

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

VME: Supports virtual real-mode extensions (VME) and protected-mode virtual interrupts.

DE: Supports breaking on I/O and on accessing debug registers DR4DR5.

DE: Supports breaking on I/O and on accessing debug registers DR4DR5.

PSE: Supports 4MB virtual memory pages and the dirty flag.

PSE: Supports 4MB virtual memory pages and the dirty flag.

TSC: Supports reading the processor’s timestamp with RDTSC.

TSC: Supports reading the processor’s timestamp with RDTSC.

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

MSR: Has model-specific registers which can be accessed with RDMSR/WRMSR.

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

PAE: Supports mapping virtual memory to physical addresses longer than 32 bits.

MCE: Defines an exception (18) for reporting internal processor errors.

MCE: Defines an exception (18) for reporting internal processor errors.

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

CX8: Supports the 64-byte CMPXCHG8B atomic instruction.

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

APIC: The processor has a built-in advanced programmable interrupt controller (APIC).

SEP: Supports the SYSENTER/SYSEXIT instructions.

SEP: Supports the SYSENTER/SYSEXIT instructions.

MTRR: Has memory type range registers.

MTRR: Has memory type range registers.

PGE: Supports global pages, which are available in all task contexts

PGE: Supports global pages, which are available in all task contexts

MCA: Supports extended features for reporting internal processor errors.

MCA: Supports extended features for reporting internal processor errors.

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

CMOV: Supports the CMOV instruction and FCMOV/FCOMI if FPU is present.

PAT: Supports page attribute tables.

PAT: Supports page attribute tables.

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

PSE-36: Supports 4MB virtual memory pages that can map to physical addresses longer than 32 bits.

PSN: Supports retrieving a processor serial number with the CPUID instruction.

PSN: Supports retrieving a processor serial number with the CPUID instruction.

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

CLFSH: Supports flushing a cache line with the CLFLUSH instruction.

DS: Supports writing debug information to memory.

DS: Supports writing debug information to memory.

ACPI: Supports thermal monitoring and power management with software.

ACPI: Supports thermal monitoring and power management with software.

MMX: Supports MMX instructions.

MMX: Supports MMX instructions.

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

FXSAVE: Supports managing FPU state with FXSAVE/FXRSTOR.

SSE: Supports SSE instructions.

SSE: Supports SSE instructions.

SSE2: Supports SSE2 instructions.

SSE2: Supports SSE2 instructions.

The processor can snoop on its own cache line. This helps deal with certain memory issues.

The processor can snoop on its own cache line. This helps deal with certain memory issues.

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

HTT: Indicates that the number of reserved APIC IDs is available with the CPUID instruction. If clear, only one ID is reserved.

TM: Has thermal monitor control circuitry (TCC).

TM: Has thermal monitor control circuitry (TCC).

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

PBE: Supports a pin notifying a stopped processor that an interrupt is pending.

SSE3: Supports SSE3 instructions.

SSE3: Supports SSE3 instructions.

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

Supports carry-less multiplication of two 64-bit integers using the PCLMULQDQ instruction.

DTES64: Supports 64-bit addresses for the debug store.

DTES64: Supports 64-bit addresses for the debug store.

MONITOR: Supports the MONITOR/MWAIT instructions.

MONITOR: Supports the MONITOR/MWAIT instructions.

DS-CPL: Supports saving the permission level with data written to the debug store.

DS-CPL: Supports saving the permission level with data written to the debug store.

VMX: Supports virtual machine extensions.

VMX: Supports virtual machine extensions.

SMX: Supports safer-mode extensions

SMX: Supports safer-mode extensions

EIST: Supports enhanced SpeedStep throttling.

EIST: Supports enhanced SpeedStep throttling.

Supports the TM2 thermal monitor interface.

Supports the TM2 thermal monitor interface.

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

SSSE3: Supports Supplemental SSE3 (SSSE3) instructions.

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

CNXT-ID: Supports setting the L1 cache to adaptive or shared mode.

SDBG: Supports an MSR for chip debugging.

SDBG: Supports an MSR for chip debugging.

FMA: Supports fused multiply-add SSE instructions.

FMA: Supports fused multiply-add SSE instructions.

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

CMPXCHG16B: Supports the 128-bit CMPXCHG16B atomic instruction.

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

Supports disabling xTPR task priority messages to the chipset through IA32_MISC_ENABLE[23].

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

PDCM: Supports a model-specific register that lists performance-monitoring and debug features.

PCID: Supports process-context IDs.

PCID: Supports process-context IDs.

DCA: Supports prefetching memory-mapped data from a device.

DCA: Supports prefetching memory-mapped data from a device.

SSE4_1: Supports SSE4.1 instructions.

SSE4_1: Supports SSE4.1 instructions.

SSE4_2: Supports SSE4.2 instructions.

SSE4_2: Supports SSE4.2 instructions.

x2APIC: Supports the enhanced “x2” interface for the APIC.

x2APIC: Supports the enhanced “x2” interface for the APIC.

Supports byte swapping with the MOVBE instruction.

Supports byte swapping with the MOVBE instruction.

Supports counting the set bits in a value with the POPCNT instruction.

Supports counting the set bits in a value with the POPCNT instruction.

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

TSC-Deadline: Supports one-shot interrupts with the APIC using the timestamp counter.

AESNI: Supports AES acceleration instructions.

AESNI: Supports AES acceleration instructions.

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

XSAVE: Supports instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

OSXSAVE: Reflects the value of [ControlRegister4::extended_state_save], indicating that the OS has enabled the XSAVE feature.

AVX: Supports AVX instructions.

AVX: Supports AVX instructions.

F16C: Supports conversion instructions for 16-bit floats.

F16C: Supports conversion instructions for 16-bit floats.

Supports random number generation with the RDRAND instruction.

Supports random number generation with the RDRAND instruction.

Retrieve the feature list from the processor using the CPUID instruction.

Trait Implementations§

Construct a new bitfield type from its underlying representation
Unwrap the bitfield into its underlying representation
Returns a copy of the value. Read more
Performs copy-assignment from source. Read more
Formats the value using the given formatter. Read more
Returns the “default value” for a type. Read more
Converts to this type from the input type.
Converts to this type from the input type.
This method tests for self and other values to be equal, and is used by ==. Read more
This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more

Auto Trait Implementations§

Blanket Implementations§

Gets the TypeId of self. Read more
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.