pub struct APICBaseRegister(/* private fields */);
Expand description
IA32_APIC_BASE
: A model-specific register that allows relocating an advanced
programmable interrupt controller (APIC)’s control structure.
See Intel ISA volume 2 §10.4.3–10.4.4.
Implementations§
Source§impl APICBaseRegister
impl APICBaseRegister
Sourcepub fn enabled(&self) -> bool
pub fn enabled(&self) -> bool
Can be cleared to disable the APIC. However, it cannot be re-enabled once disabled with this mechanism.
Sourcepub fn x2_interface(&self) -> bool
pub fn x2_interface(&self) -> bool
Enable the APIC’s
Sourcepub fn bootstrap_processor(&self) -> bool
pub fn bootstrap_processor(&self) -> bool
Indicates that this core was designated as the bootstrap processor for single-threaded operation on startup.
Sourcepub fn set_enabled(&mut self, value: bool)
pub fn set_enabled(&mut self, value: bool)
Can be cleared to disable the APIC. However, it cannot be re-enabled once disabled with this mechanism.
Sourcepub fn with_enabled(&mut self, value: bool) -> Self
pub fn with_enabled(&mut self, value: bool) -> Self
Can be cleared to disable the APIC. However, it cannot be re-enabled once disabled with this mechanism.
Sourcepub fn set_x2_interface(&mut self, value: bool)
pub fn set_x2_interface(&mut self, value: bool)
Enable the APIC’s
Sourcepub fn with_x2_interface(&mut self, value: bool) -> Self
pub fn with_x2_interface(&mut self, value: bool) -> Self
Enable the APIC’s
Sourcepub fn set_bootstrap_processor(&mut self, value: bool)
pub fn set_bootstrap_processor(&mut self, value: bool)
Indicates that this core was designated as the bootstrap processor for single-threaded operation on startup.
Sourcepub fn with_bootstrap_processor(&mut self, value: bool) -> Self
pub fn with_bootstrap_processor(&mut self, value: bool) -> Self
Indicates that this core was designated as the bootstrap processor for single-threaded operation on startup.
Source§impl APICBaseRegister
impl APICBaseRegister
Sourcepub const DEFAULT_ADDRESS: usize = 4_276_092_928usize
pub const DEFAULT_ADDRESS: usize = 4_276_092_928usize
The default APIC base address when the processor is reset.
Sourcepub fn set_address(&mut self, address: usize)
pub fn set_address(&mut self, address: usize)
Update the base address of the APIC’s registers.
Trait Implementations§
Source§impl Bitfield<u64> for APICBaseRegister
impl Bitfield<u64> for APICBaseRegister
Source§impl Clone for APICBaseRegister
impl Clone for APICBaseRegister
Source§fn clone(&self) -> APICBaseRegister
fn clone(&self) -> APICBaseRegister
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
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