Struct tartan_arch::x86_common::ControlRegister0

#[repr(transparent)]
pub struct ControlRegister0(_);

Available on x86 or x86-64 only.

CR0: System control register with flags affecting protection, paging, and FPU behavior.

Getters and setters for this structure only access a value in memory, not the register itself. Use the get and set methods to work with the actual register.

Implementations

impl ControlRegister0

pub fn paging(&self) -> bool

CR0.PG: Enable paging. Requires protected_mode.

pub fn cache_disabled(&self) -> bool

CR0.CD: Disable all memory caching.

pub fn cache_not_write_through(&self) -> bool

CR0.NW: Disable write-back/write-through caching.

pub fn alignment_check_mask(&self) -> bool

CR0.AM: Enables strict alignment checks for memory access, in combination with FlagRegister::alignment_check_or_access_control.

pub fn write_protect(&self) -> bool

CR0.WP: Enforce read-only pages even in privilege levels 0–2. They are always enforced in level 3.

pub fn native_fpu_error(&self) -> bool

CR0.NE: Use internal error mechanism for FPU errors, rather than DOS-style.

pub fn fpu_extension_type(&self) -> bool

CR0.ET: On 386/486, 387 FPU instructions are supported if set. Always set on modern processors.

pub fn task_switched_without_fpu_state(&self) -> bool

CR0.TS: Set by processor when task was switched but FPU context has not been saved yet.

Used to save work when the new task does not alter the FPU state. When an FPU instruction is executed with this flag set, the processor raises an exception that allows the OS to save the FPU state. This behavior can be altered by other flags. See monitor_fpu_state.

pub fn fpu_emulation(&self) -> bool

CR0.EM: Trigger an exception on all FPU instructions. Used to support software emulation.

pub fn monitor_fpu(&self) -> bool

CR0.MP: Enable exception behavior described for the CR0.TS flag for the (F)WAIT instruction.

pub fn protected_mode(&self) -> bool

Enable protected mode. Does not enable paging on its own. See paging.

pub fn set_paging(&mut self, value: bool)

CR0.PG: Enable paging. Requires protected_mode.

pub fn with_paging(&mut self, value: bool) -> Self

CR0.PG: Enable paging. Requires protected_mode.

pub fn set_cache_disabled(&mut self, value: bool)

CR0.CD: Disable all memory caching.

pub fn with_cache_disabled(&mut self, value: bool) -> Self

CR0.CD: Disable all memory caching.

pub fn set_cache_not_write_through(&mut self, value: bool)

CR0.NW: Disable write-back/write-through caching.

pub fn with_cache_not_write_through(&mut self, value: bool) -> Self

CR0.NW: Disable write-back/write-through caching.

pub fn set_alignment_check_mask(&mut self, value: bool)

CR0.AM: Enables strict alignment checks for memory access, in combination with FlagRegister::alignment_check_or_access_control.

pub fn with_alignment_check_mask(&mut self, value: bool) -> Self

CR0.AM: Enables strict alignment checks for memory access, in combination with FlagRegister::alignment_check_or_access_control.

pub fn set_write_protect(&mut self, value: bool)

CR0.WP: Enforce read-only pages even in privilege levels 0–2. They are always enforced in level 3.

pub fn with_write_protect(&mut self, value: bool) -> Self

CR0.WP: Enforce read-only pages even in privilege levels 0–2. They are always enforced in level 3.

pub fn set_native_fpu_error(&mut self, value: bool)

CR0.NE: Use internal error mechanism for FPU errors, rather than DOS-style.

pub fn with_native_fpu_error(&mut self, value: bool) -> Self

CR0.NE: Use internal error mechanism for FPU errors, rather than DOS-style.

pub fn set_fpu_extension_type(&mut self, value: bool)

CR0.ET: On 386/486, 387 FPU instructions are supported if set. Always set on modern processors.

pub fn with_fpu_extension_type(&mut self, value: bool) -> Self

CR0.ET: On 386/486, 387 FPU instructions are supported if set. Always set on modern processors.

pub fn set_task_switched_without_fpu_state(&mut self, value: bool)

CR0.TS: Set by processor when task was switched but FPU context has not been saved yet.

Used to save work when the new task does not alter the FPU state. When an FPU instruction is executed with this flag set, the processor raises an exception that allows the OS to save the FPU state. This behavior can be altered by other flags. See monitor_fpu_state.

pub fn with_task_switched_without_fpu_state(&mut self, value: bool) -> Self

CR0.TS: Set by processor when task was switched but FPU context has not been saved yet.

Used to save work when the new task does not alter the FPU state. When an FPU instruction is executed with this flag set, the processor raises an exception that allows the OS to save the FPU state. This behavior can be altered by other flags. See monitor_fpu_state.

pub fn set_fpu_emulation(&mut self, value: bool)

CR0.EM: Trigger an exception on all FPU instructions. Used to support software emulation.

pub fn with_fpu_emulation(&mut self, value: bool) -> Self

CR0.EM: Trigger an exception on all FPU instructions. Used to support software emulation.

pub fn set_monitor_fpu(&mut self, value: bool)

CR0.MP: Enable exception behavior described for the CR0.TS flag for the (F)WAIT instruction.

pub fn with_monitor_fpu(&mut self, value: bool) -> Self

CR0.MP: Enable exception behavior described for the CR0.TS flag for the (F)WAIT instruction.

pub fn set_protected_mode(&mut self, value: bool)

Enable protected mode. Does not enable paging on its own. See paging.

pub fn with_protected_mode(&mut self, value: bool) -> Self

Enable protected mode. Does not enable paging on its own. See paging.

impl ControlRegister0

pub fn get() -> Self

Retrieve the current value of this register

pub unsafe fn set(value: Self)

Update the register to the given value.

Safety

Altering certain system flags can have dramatic effects on the execution of this and other programs, including memory safety.

impl ControlRegister0

pub unsafe fn clear_task_switched_without_fpu_state()

Directly clear the task_switched_without_fpu_state flag in this register using a single instruction.

Safety

Clearing this flag when inappropriate may clobber FPU state and potentially affect memory safety.

Trait Implementations

impl Bitfield<usize> for ControlRegister0

fn new(value: T) -> Self

Construct a new bitfield type from its underlying representation

fn value(self) -> T

Unwrap the bitfield into its underlying representation

impl Clone for ControlRegister0

fn clone(&self) -> ControlRegister0

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ControlRegister0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ControlRegister0

fn default() -> ControlRegister0

Returns the “default value” for a type.

impl From<ControlRegister0> for usize

fn from(val: ControlRegister0) -> Self

Converts to this type from the input type.

impl From<usize> for ControlRegister0

fn from(val: usize) -> Self

Converts to this type from the input type.

impl PartialEq<ControlRegister0> for ControlRegister0

fn eq(&self, other: &ControlRegister0) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for ControlRegister0

impl Eq for ControlRegister0

impl StructuralEq for ControlRegister0

impl StructuralPartialEq for ControlRegister0