Struct tartan_arch::x86_common::ExtendedControlRegister0

pub struct ExtendedControlRegister0(/* private fields */);

Available on x86 or x86-64 only.

XCR0: System control flags that indicate OS support for context management for various registers with the XSAVE feature.

Getters and setters for this structure only access a value in memory, not the register itself. Use the get and set methods to work with the actual register.

Requires BasicFeatures::extended_state_save.

Implementations

impl ExtendedControlRegister0

pub fn fpu(&self) -> bool

XCR0.X87: Hardcoded to 1.

pub fn sse(&self) -> bool

XCR0.SSE: Manage SSE state with XSAVE, including the XMM registers.

pub fn avx_256(&self) -> bool

XCR0.AVX: Manage 256-bit AVX state in upper halves of the YMM registers with XSAVE.

Requires sse. The lower halves of these registers are equivalent to XMM and are covered by that flag.

pub fn mpx_bounds(&self) -> bool

XCR0.BNDREG: Manage MPX bounds registers with XSAVE.

Requires mpx_bound_config_status.

pub fn mpx_bound_config_status(&self) -> bool

XCR0.BNDCSR: Manage MPX config and status registers with XSAVE.

Requires mpx_bounds.

pub fn avx_512_opmask(&self) -> bool

XCR0.OPMASK: Manage AVX-512 opmask registers with XSAVE.

Requires the other avx_512_* flags.

pub fn avx_512(&self) -> bool

XCR0.ZMM_Hi256: Manage 512-bit AVX state in the upper halves of the ZMM registers up to ZMM15 with XSAVE.

Registers ZMM8–ZMM15 are available in 64-bit mode only, so this only applies up to ZMM7 in 32-bit mode.

Requires avx_256 and the other avx_512_* flags. The lower halves of these registers are equivalent to YMM and are covered by avx_256(Self::avx_256).

pub fn avx_512_extended(&self) -> bool

Available on x86-64 only.

XCR0.Hi16_ZMM: Manage AVX-512 state in ZMM16–ZMM31 with XSAVE.

These registers are only available in 64-bit mode.

Requires the other avx_512_* flags.

pub fn protection_key_rights(&self) -> bool

XCR0.PKRU: Manage protection key rights registers with XSAVE.

pub fn set_fpu(&mut self, value: bool)

XCR0.X87: Hardcoded to 1.

pub fn with_fpu(&mut self, value: bool) -> Self

XCR0.X87: Hardcoded to 1.

pub fn set_sse(&mut self, value: bool)

XCR0.SSE: Manage SSE state with XSAVE, including the XMM registers.

pub fn with_sse(&mut self, value: bool) -> Self

XCR0.SSE: Manage SSE state with XSAVE, including the XMM registers.

pub fn set_avx_256(&mut self, value: bool)

XCR0.AVX: Manage 256-bit AVX state in upper halves of the YMM registers with XSAVE.

Requires sse. The lower halves of these registers are equivalent to XMM and are covered by that flag.

pub fn with_avx_256(&mut self, value: bool) -> Self

XCR0.AVX: Manage 256-bit AVX state in upper halves of the YMM registers with XSAVE.

Requires sse. The lower halves of these registers are equivalent to XMM and are covered by that flag.

pub fn set_mpx_bounds(&mut self, value: bool)

XCR0.BNDREG: Manage MPX bounds registers with XSAVE.

Requires mpx_bound_config_status.

pub fn with_mpx_bounds(&mut self, value: bool) -> Self

XCR0.BNDREG: Manage MPX bounds registers with XSAVE.

Requires mpx_bound_config_status.

pub fn set_mpx_bound_config_status(&mut self, value: bool)

XCR0.BNDCSR: Manage MPX config and status registers with XSAVE.

Requires mpx_bounds.

pub fn with_mpx_bound_config_status(&mut self, value: bool) -> Self

XCR0.BNDCSR: Manage MPX config and status registers with XSAVE.

Requires mpx_bounds.

pub fn set_avx_512_opmask(&mut self, value: bool)

XCR0.OPMASK: Manage AVX-512 opmask registers with XSAVE.

Requires the other avx_512_* flags.

pub fn with_avx_512_opmask(&mut self, value: bool) -> Self

XCR0.OPMASK: Manage AVX-512 opmask registers with XSAVE.

Requires the other avx_512_* flags.

pub fn set_avx_512(&mut self, value: bool)

XCR0.ZMM_Hi256: Manage 512-bit AVX state in the upper halves of the ZMM registers up to ZMM15 with XSAVE.

Registers ZMM8–ZMM15 are available in 64-bit mode only, so this only applies up to ZMM7 in 32-bit mode.

Requires avx_256 and the other avx_512_* flags. The lower halves of these registers are equivalent to YMM and are covered by avx_256(Self::avx_256).

pub fn with_avx_512(&mut self, value: bool) -> Self

XCR0.ZMM_Hi256: Manage 512-bit AVX state in the upper halves of the ZMM registers up to ZMM15 with XSAVE.

Registers ZMM8–ZMM15 are available in 64-bit mode only, so this only applies up to ZMM7 in 32-bit mode.

Requires avx_256 and the other avx_512_* flags. The lower halves of these registers are equivalent to YMM and are covered by avx_256(Self::avx_256).

pub fn set_avx_512_extended(&mut self, value: bool)

Available on x86-64 only.

XCR0.Hi16_ZMM: Manage AVX-512 state in ZMM16–ZMM31 with XSAVE.

These registers are only available in 64-bit mode.

Requires the other avx_512_* flags.

pub fn with_avx_512_extended(&mut self, value: bool) -> Self

Available on x86-64 only.

XCR0.Hi16_ZMM: Manage AVX-512 state in ZMM16–ZMM31 with XSAVE.

These registers are only available in 64-bit mode.

Requires the other avx_512_* flags.

pub fn set_protection_key_rights(&mut self, value: bool)

XCR0.PKRU: Manage protection key rights registers with XSAVE.

pub fn with_protection_key_rights(&mut self, value: bool) -> Self

XCR0.PKRU: Manage protection key rights registers with XSAVE.

impl ExtendedControlRegister0

pub fn get() -> Self

Retrieve the current value of this register

pub unsafe fn set(value: Self)

Update the register to the given value.

Safety

Altering certain system flags can have dramatic effects on the execution of this and other programs, including memory safety.

Trait Implementations

impl Bitfield<u64> for ExtendedControlRegister0

fn new(value: T) -> Self

Construct a new bitfield type from its underlying representation

fn value(self) -> T

Unwrap the bitfield into its underlying representation

impl Clone for ExtendedControlRegister0

fn clone(&self) -> ExtendedControlRegister0

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ExtendedControlRegister0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ExtendedControlRegister0

fn default() -> ExtendedControlRegister0

Returns the “default value” for a type.

impl From<ExtendedControlRegister0> for u64

fn from(val: ExtendedControlRegister0) -> Self

Converts to this type from the input type.

impl From<u64> for ExtendedControlRegister0

fn from(val: u64) -> Self

Converts to this type from the input type.

impl PartialEq for ExtendedControlRegister0

fn eq(&self, other: &ExtendedControlRegister0) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for ExtendedControlRegister0

impl Eq for ExtendedControlRegister0

impl StructuralPartialEq for ExtendedControlRegister0