Struct tartan_arch::x86_common::ControlRegister4

source ·
pub struct ControlRegister4(/* private fields */);
Available on x86 or x86-64 only.
Expand description

CR4: Miscellaneous system control flags.

Getters and setters for this structure only access a value in memory, not the register itself. Use the get and set methods to work with the actual register.

Implementations§

source§

impl ControlRegister4

source

pub fn virtual_8086_extensions(&self) -> bool

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn protected_virtual_interrupts(&self) -> bool

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn timestamp_disabled(&self) -> bool

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

source

pub fn debugging_extensions(&self) -> bool

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

source

pub fn page_size_extensions(&self) -> bool

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

source

pub fn physical_address_extension(&self) -> bool

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

source

pub fn machine_check_exception(&self) -> bool

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

source

pub fn global_pages(&self) -> bool

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

source

pub fn performance_counter(&self) -> bool

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

source

pub fn sse_and_fpu_save(&self) -> bool

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

source

pub fn simd_exceptions(&self) -> bool

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

source

pub fn restrict_user_mode_instructions(&self) -> bool

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

source

pub fn five_level_paging(&self) -> bool

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

source

pub fn virtual_machine_extensions(&self) -> bool

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

source

pub fn safer_mode_extensions(&self) -> bool

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

source

pub fn extended_base_registers(&self) -> bool

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

source

pub fn process_context_ids(&self) -> bool

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

source

pub fn extended_state_save(&self) -> bool

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

source

pub fn supervisor_execution_prevention(&self) -> bool

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

source

pub fn supervisor_access_prevention(&self) -> bool

CR4.SMAP: Enable access prevention in privilege levels 0–2.

source

pub fn user_protection_keys(&self) -> bool

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

source

pub fn control_flow_enforcement(&self) -> bool

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

source

pub fn supervisor_protection_keys(&self) -> bool

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

source

pub fn set_virtual_8086_extensions(&mut self, value: bool)

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn with_virtual_8086_extensions(&mut self, value: bool) -> Self

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn set_protected_virtual_interrupts(&mut self, value: bool)

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn with_protected_virtual_interrupts(&mut self, value: bool) -> Self

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

source

pub fn set_timestamp_disabled(&mut self, value: bool)

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

source

pub fn with_timestamp_disabled(&mut self, value: bool) -> Self

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

source

pub fn set_debugging_extensions(&mut self, value: bool)

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

source

pub fn with_debugging_extensions(&mut self, value: bool) -> Self

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

source

pub fn set_page_size_extensions(&mut self, value: bool)

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

source

pub fn with_page_size_extensions(&mut self, value: bool) -> Self

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

source

pub fn set_physical_address_extension(&mut self, value: bool)

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

source

pub fn with_physical_address_extension(&mut self, value: bool) -> Self

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

source

pub fn set_machine_check_exception(&mut self, value: bool)

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

source

pub fn with_machine_check_exception(&mut self, value: bool) -> Self

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

source

pub fn set_global_pages(&mut self, value: bool)

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

source

pub fn with_global_pages(&mut self, value: bool) -> Self

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

source

pub fn set_performance_counter(&mut self, value: bool)

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

source

pub fn with_performance_counter(&mut self, value: bool) -> Self

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

source

pub fn set_sse_and_fpu_save(&mut self, value: bool)

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

source

pub fn with_sse_and_fpu_save(&mut self, value: bool) -> Self

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

source

pub fn set_simd_exceptions(&mut self, value: bool)

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

source

pub fn with_simd_exceptions(&mut self, value: bool) -> Self

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

source

pub fn set_restrict_user_mode_instructions(&mut self, value: bool)

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

source

pub fn with_restrict_user_mode_instructions(&mut self, value: bool) -> Self

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

source

pub fn set_five_level_paging(&mut self, value: bool)

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

source

pub fn with_five_level_paging(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

source

pub fn set_virtual_machine_extensions(&mut self, value: bool)

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

source

pub fn with_virtual_machine_extensions(&mut self, value: bool) -> Self

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

source

pub fn set_safer_mode_extensions(&mut self, value: bool)

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

source

pub fn with_safer_mode_extensions(&mut self, value: bool) -> Self

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

source

pub fn set_extended_base_registers(&mut self, value: bool)

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

source

pub fn with_extended_base_registers(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

source

pub fn set_process_context_ids(&mut self, value: bool)

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

source

pub fn with_process_context_ids(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

source

pub fn set_extended_state_save(&mut self, value: bool)

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

source

pub fn with_extended_state_save(&mut self, value: bool) -> Self

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

source

pub fn set_supervisor_execution_prevention(&mut self, value: bool)

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

source

pub fn with_supervisor_execution_prevention(&mut self, value: bool) -> Self

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

source

pub fn set_supervisor_access_prevention(&mut self, value: bool)

CR4.SMAP: Enable access prevention in privilege levels 0–2.

source

pub fn with_supervisor_access_prevention(&mut self, value: bool) -> Self

CR4.SMAP: Enable access prevention in privilege levels 0–2.

source

pub fn set_user_protection_keys(&mut self, value: bool)

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

source

pub fn with_user_protection_keys(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

source

pub fn set_control_flow_enforcement(&mut self, value: bool)

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

source

pub fn with_control_flow_enforcement(&mut self, value: bool) -> Self

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

source

pub fn set_supervisor_protection_keys(&mut self, value: bool)

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

source

pub fn with_supervisor_protection_keys(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

source§

impl ControlRegister4

source

pub fn get() -> Self

Retrieve the current value of this register

source

pub unsafe fn set(value: Self)

Update the register to the given value.

§Safety

Altering certain system flags can have dramatic effects on the execution of this and other programs, including memory safety.

Trait Implementations§

source§

impl Bitfield<usize> for ControlRegister4

§

fn new(value: T) -> Self

Construct a new bitfield type from its underlying representation
§

fn value(self) -> T

Unwrap the bitfield into its underlying representation
source§

impl Clone for ControlRegister4

source§

fn clone(&self) -> ControlRegister4

Returns a copy of the value. Read more
1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
source§

impl Debug for ControlRegister4

source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
source§

impl Default for ControlRegister4

source§

fn default() -> ControlRegister4

Returns the “default value” for a type. Read more
source§

impl From<ControlRegister4> for usize

source§

fn from(val: ControlRegister4) -> Self

Converts to this type from the input type.
source§

impl From<usize> for ControlRegister4

source§

fn from(val: usize) -> Self

Converts to this type from the input type.
source§

impl PartialEq for ControlRegister4

source§

fn eq(&self, other: &ControlRegister4) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
source§

impl Copy for ControlRegister4

source§

impl Eq for ControlRegister4

source§

impl StructuralPartialEq for ControlRegister4

Auto Trait Implementations§

Blanket Implementations§

source§

impl<T> Any for T
where T: 'static + ?Sized,

source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
source§

impl<T> Borrow<T> for T
where T: ?Sized,

source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
source§

impl<T> CloneToUninit for T
where T: Clone,

source§

default unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
source§

impl<T> CloneToUninit for T
where T: Copy,

source§

unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
source§

impl<T> From<T> for T

source§

fn from(t: T) -> T

Returns the argument unchanged.

source§

impl<T, U> Into<U> for T
where U: From<T>,

source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source§

impl<T, U> TryFrom<U> for T
where U: Into<T>,

§

type Error = Infallible

The type returned in the event of a conversion error.
source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
source§

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.