#[repr(transparent)]
pub struct ControlRegister4(_);
Available on x86 or x86-64 only.
Expand description

CR4: Miscellaneous system control flags.

Getters and setters for this structure only access a value in memory, not the register itself. Use the get and set methods to work with the actual register.

Implementations§

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

CR4.SMAP: Enable access prevention in privilege levels 0–2.

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.PVI: Enable virtual interrupts in protected mode.

Requires BasicFeatures::virtual_8086_extensions.

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

CR4.SMAP: Enable access prevention in privilege levels 0–2.

CR4.SMAP: Enable access prevention in privilege levels 0–2.

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

Retrieve the current value of this register

Update the register to the given value.

Safety

Altering certain system flags can have dramatic effects on the execution of this and other programs, including memory safety.

Trait Implementations§

Construct a new bitfield type from its underlying representation
Unwrap the bitfield into its underlying representation
Returns a copy of the value. Read more
Performs copy-assignment from source. Read more
Formats the value using the given formatter. Read more
Returns the “default value” for a type. Read more
Converts to this type from the input type.
Converts to this type from the input type.
This method tests for self and other values to be equal, and is used by ==. Read more
This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more

Auto Trait Implementations§

Blanket Implementations§

Gets the TypeId of self. Read more
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.