Struct tartan_arch::x86_common::ControlRegister4

impl ControlRegister4

pub fn virtual_8086_extensions(&self) -> bool

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

pub fn protected_virtual_interrupts(&self) -> bool

CR4.PVI: Enable virtual interrupts in protected mode.

pub fn timestamp_disabled(&self) -> bool

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

pub fn debugging_extensions(&self) -> bool

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

pub fn page_size_extensions(&self) -> bool

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

pub fn physical_address_extension(&self) -> bool

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

pub fn machine_check_exception(&self) -> bool

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

pub fn global_pages(&self) -> bool

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

pub fn performance_counter(&self) -> bool

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

pub fn sse_and_fpu_save(&self) -> bool

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

pub fn simd_exceptions(&self) -> bool

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

pub fn restrict_user_mode_instructions(&self) -> bool

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

pub fn five_level_paging(&self) -> bool

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

pub fn virtual_machine_extensions(&self) -> bool

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

pub fn safer_mode_extensions(&self) -> bool

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

pub fn extended_base_registers(&self) -> bool

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

pub fn process_context_ids(&self) -> bool

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

pub fn extended_state_save(&self) -> bool

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

pub fn supervisor_execution_prevention(&self) -> bool

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

pub fn supervisor_access_prevention(&self) -> bool

CR4.SMAP: Enable access prevention in privilege levels 0–2.

pub fn user_protection_keys(&self) -> bool

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

pub fn control_flow_enforcement(&self) -> bool

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

pub fn supervisor_protection_keys(&self) -> bool

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

pub fn set_virtual_8086_extensions(&mut self, value: bool)

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

pub fn with_virtual_8086_extensions(&mut self, value: bool) -> Self

CR4.VME: Enable interrupts and exception handling in virtual real-mode.

pub fn set_protected_virtual_interrupts(&mut self, value: bool)

CR4.PVI: Enable virtual interrupts in protected mode.

pub fn with_protected_virtual_interrupts(&mut self, value: bool) -> Self

CR4.PVI: Enable virtual interrupts in protected mode.

pub fn set_timestamp_disabled(&mut self, value: bool)

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

pub fn with_timestamp_disabled(&mut self, value: bool) -> Self

CR4.TSD: Disable access to processor timestamp counter except in privilege level 0.

Requires [BasicFeatures::timestamp_counter].

pub fn set_debugging_extensions(&mut self, value: bool)

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

pub fn with_debugging_extensions(&mut self, value: bool) -> Self

CR4.DE: Enable newer debug register scheme where DR4 and DR5 are unavailable.

When this flag is clear, they are equivalent to DR6 and DR7.

Requires BasicFeatures::debugging_extensions.

pub fn set_page_size_extensions(&mut self, value: bool)

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

pub fn with_page_size_extensions(&mut self, value: bool) -> Self

CR4.PSE: Support large pages (4MB). Applies to 32-bit mode only.

When this flag is clear in 32-bit mode, pages are always 4KB. Large pages are always enabled in 64-bit mode.

Requires [BasicFeatures::page_size_extensions].

pub fn set_physical_address_extension(&mut self, value: bool)

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

pub fn with_physical_address_extension(&mut self, value: bool) -> Self

CR4.PAE: Enable pages to map to physical addresses larger than 32-bits.

Required for 64-bit mode.

Requires BasicFeatures::physical_address_extension.

pub fn set_machine_check_exception(&mut self, value: bool)

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

pub fn with_machine_check_exception(&mut self, value: bool) -> Self

CR4.MCE: Enable machine-check exception.

Requires BasicFeatures::machine_check_exception.

pub fn set_global_pages(&mut self, value: bool)

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

pub fn with_global_pages(&mut self, value: bool) -> Self

CR4.PGE: Enable global pages, which are shared across task contexts.

Requires BasicFeatures::global_pages.

pub fn set_performance_counter(&mut self, value: bool)

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

pub fn with_performance_counter(&mut self, value: bool) -> Self

CR4.PCE: Allow access to performance monitoring counter in privilege levels 1–3 (always accessible in level 0).

pub fn set_sse_and_fpu_save(&mut self, value: bool)

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

pub fn with_sse_and_fpu_save(&mut self, value: bool) -> Self

CR4.OSFXSR: Enable the FXSAVE/FXRSTOR and SSE instructions, if present.

These instructions require special support from the operating system.

Requires BasicFeatures::fpu_save.

pub fn set_simd_exceptions(&mut self, value: bool)

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

pub fn with_simd_exceptions(&mut self, value: bool) -> Self

CR4.OSXMMEXCPT: Enable unmasked SIMD floating-point exception handling for SSE instructions.

This requires special support from the operating system.

pub fn set_restrict_user_mode_instructions(&mut self, value: bool)

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

pub fn with_restrict_user_mode_instructions(&mut self, value: bool) -> Self

CR4.UMIP: Prevent access to instructions that allow reads from descriptor/task registers, except in privilege level 0.

pub fn set_five_level_paging(&mut self, value: bool)

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

pub fn with_five_level_paging(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.LA57: Support 57-bit addresses using 5-level paging in 64-bit mode.

pub fn set_virtual_machine_extensions(&mut self, value: bool)

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

pub fn with_virtual_machine_extensions(&mut self, value: bool) -> Self

CR4.VMX (Intel-only): Enable virtual machine extensions.

Requires BasicFeatures::virtual_machine_extensions.

pub fn set_safer_mode_extensions(&mut self, value: bool)

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

pub fn with_safer_mode_extensions(&mut self, value: bool) -> Self

CR4.SME (Intel-only): Enable safer-mode extensions.

Requires BasicFeatures::safer_mode_extensions.

pub fn set_extended_base_registers(&mut self, value: bool)

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

pub fn with_extended_base_registers(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.FSGSBASE: Enable instructions to load/store the FS and GS base registers with 32/64-bit values in 64-bit mode.

pub fn set_process_context_ids(&mut self, value: bool)

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

pub fn with_process_context_ids(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PCIDE: Enable process-context identifiers (PCID) in 64-bit mode.

Requires BasicFeatures::process_context_ids.

pub fn set_extended_state_save(&mut self, value: bool)

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

pub fn with_extended_state_save(&mut self, value: bool) -> Self

CR4.OSXSAVE: Enable instructions for saving and restoring extended processor state (FPU/MMX/SSE/AVX).

These instructions require special support from the operating system.

Requires BasicFeatures::extended_state_save.

pub fn set_supervisor_execution_prevention(&mut self, value: bool)

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

pub fn with_supervisor_execution_prevention(&mut self, value: bool) -> Self

CR4.SMEP: Enable execution prevention in privilege levels 0–2.

pub fn set_supervisor_access_prevention(&mut self, value: bool)

CR4.SMAP: Enable access prevention in privilege levels 0–2.

pub fn with_supervisor_access_prevention(&mut self, value: bool) -> Self

CR4.SMAP: Enable access prevention in privilege levels 0–2.

pub fn set_user_protection_keys(&mut self, value: bool)

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

pub fn with_user_protection_keys(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PKE: Use page protection keys in 64-bit mode to control access from privilege level 3.

pub fn set_control_flow_enforcement(&mut self, value: bool)

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

pub fn with_control_flow_enforcement(&mut self, value: bool) -> Self

CR4.CET (Intel-only): Enable control-flow enforcement technology. Requires ControlRegister0::write_protect.

pub fn set_supervisor_protection_keys(&mut self, value: bool)

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

pub fn with_supervisor_protection_keys(&mut self, value: bool) -> Self

Available on x86-64 only.

CR4.PKS (Intel-only): Use page protection keys in 64-bit mode to control access from privilege levels 0-2.

impl ControlRegister4

pub fn get() -> Self

Retrieve the current value of this register

pub unsafe fn set(value: Self)

Update the register to the given value.

Safety

Altering certain system flags can have dramatic effects on the execution of this and other programs, including memory safety.

Trait Implementations§

impl Bitfield<usize> for ControlRegister4

fn new(value: T) -> Self

Construct a new bitfield type from its underlying representation

fn value(self) -> T

Unwrap the bitfield into its underlying representation

impl Clone for ControlRegister4

fn clone(&self) -> ControlRegister4

Returns a copy of the value. Read more

1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl Debug for ControlRegister4

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl Default for ControlRegister4

fn default() -> ControlRegister4

Returns the “default value” for a type. Read more

impl From<ControlRegister4> for usize

fn from(val: ControlRegister4) -> Self

Converts to this type from the input type.

impl From<usize> for ControlRegister4

fn from(val: usize) -> Self

Converts to this type from the input type.

impl PartialEq<ControlRegister4> for ControlRegister4

fn eq(&self, other: &ControlRegister4) -> bool

This method tests for self and other values to be equal, and is used by ==. Read more

1.0.0 · source§

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more

impl StructuralPartialEq for ControlRegister4

Auto Trait Implementations§

impl RefUnwindSafe for ControlRegister4

impl Send for ControlRegister4

impl Sync for ControlRegister4

impl Unpin for ControlRegister4

impl UnwindSafe for ControlRegister4

Blanket Implementations§

impl<T> Any for Twhere
T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for Twhere
T: ?Sized,

const: unstable · source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for Twhere
T: ?Sized,

const: unstable · source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> From<T> for T

const: unstable · source§

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into for Twhere
U: From<T>,

const: unstable · source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T, U> TryFrom for Twhere
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

const: unstable · source§

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

impl<T, U> TryInto for Twhere
U: TryFrom<T>,